Paul Franzon's website

Design of 3D ICs

  • Heterogeneous Processor Stack – die photo, layouts of the two chips and SEM Cross-section
  • Employment of 3DIC and Hybrid Bonding in Split Fabrication for Design Obfuscation – Concept, Die images and cross-section
  • Metrics for Chiplet Interfaces
  • Chipletized Machine Learning System
  • 3D Memory on Logic for Machine Learning

Selected 3DIC Papers

BOOKS

  • P. Franzon, E. Martissen, M. Bakir (eds), “3DIC Handbook Design and Test” (Wiley), 2019.
  • D. Doane and P. Franzon: Multichip Modules: Basics and Alternatives, 1993, by Van Nostrand Rheinhold.
  • J-D Cho and P.D. Franzon, High Performance Design Automation for Multi-Chip Modules and Packages, 1996, World Scientific.

BOOK CHAPTERS

  • P. Franzon, “3D Integration: Technology and Design,” in “3D Integration in VLSI Circuits,” in K. Sakuma (ed), 2018.
  • P. Franzon, “Electronic Design Automation for 3D”, in “3D Handbook Design and Test,”, P. Franzon, E. Martissen, M. Bakir (eds), (Wiley), 2019.
  • P. Franzon, “3D Design Styles”, in “3D Handbook Design and Test,”, P. Franzon, E. Martissen, M. Bakir (eds), (Wiley), 2019.
  • P. Franzon, Design for 3-D Integration, 3-D IC Integration: Technology and Applications, P. Garrou, P. Ramm, C. Bower, (editors), Wiley VCH, May 2008.
  • P. Franzon, Chip-Package Codesign, in The Handbook for EDA of Electronic Circuits, Lou Scheffer, Luciano Lavagno and Grant Martin (editors), CRC Press, 2005.

JOURNAL PUBLICATIONS

  1. T. Nigussie, J. C. Schabel, S. Lipa, L. McIlrath, R. Patti and P. Franzon, “Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 9, pp. 1230-1243, Sept. 2022. doi: 10.1109/TVLSI.2022.3179304
  2. N. Zannat and P. D. Franzon, “Asymmetric Transformer Design With Multiband Frequency Response for Simultaneous Power and Data Transfer,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 4, pp. 644-653, April 2020.
  3. J. B. Park, W. R. Davis and P. D. Franzon, “3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 2, pp. 756-768, Feb. 2019.
  4. J. C. Schabel and P. D. Franzon, “Exploring the Tradeoffs of Application-Specific Processing,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 531-542, Sept. 2018.
  5. G. Charles and P. D. Franzon, “A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 5, no. 4, pp. 541-550, April 2015
  6. Bapat, O.A.; Franzon, P.D.; Fastow, R.M., “A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.PP, no.99, pp.1,1, 2014.
  7. Xi Chen; Ting Zhu; Davis, W.R.; Franzon, P.D., “Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits,” Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.4, no.11, pp.1862,1870, Nov. 2014
  8. Gadfort, P.; Franzon, P.D., “Millimeter-Scale True 3-D Antenna-in-Package Structures for Near-Field Power Transfer,” Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.4, no.10, pp.1574,1581, Oct. 2014
  9. Priyadarshi, S.; Davis, W.R.; Steer, M.B.; Franzon, P.D., “Thermal Pathfinding for 3-D ICs,” Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.4, no.7, pp.1159,1168, July 2014
  10. R.T. Harris. S. Priyadarshi, S. Melamed, C. Ortega, M. Rajit, S. Doorly, N. Kriplani, W. Davis, P. Franzon, M. Steer, “A transient electrothermal analysis of three-dimensional integrated circuits,” in IEEE Trans. CPMT, Vol. 2, No. 4, 2012, pp. 660-667.
  11. . Melamed, T. Thorolfsson, R.T. Harris, S. Priyadarshi, P.D. Franzon, M.B. Steer, W.R. Davis, “Junction level thermal analysis of 3-D integrated circuits using high definition power blurring,” in IEEE Trans CAD, Vol. 31, No. 5, 2012, pp. 676-689.
  12. S. Priyadarshi, T.R. Harris, S. Melamed, C. Otero, N.M. Kriplani, C.E. Christoffersen, R. Manohar, S.R. Dooley, W.R.Davis, P.D. Franzon, M.B. Steer, “Dynamic Electrothermal Simulation of Three-Dimensional Circuits Using Standard Cell Macromodels,” in IET Circuits, Devices, and Systems, Vol. 6., No. 1., 2012, pp. 35-44.
  13. T.R. Harris, S. Priyadarshi, S. Melamed, C. Ortega, R. Manohar, S.R. Dooley, N.M. Kriplani, W.R. Davis, P.D. Franzon, M.B. Steer, “A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits,” in IEEE Trans CPMT, Vol. P, Issue 99, 2012, pp. 1.
  14. T. Thorolffson, N. Moezzi-Madani, P.D. Franzon, “Reconfigurable five-layer three-dimensional integrated memory on logic synthetic aperture radar processor, in IET Computers and Digital Techniques, Vol. 5, Issue 3, 2011, pp. 198-204.
  15. W. Davis, E. Oh, A. Sule, T. Thorolfsson, and P.D. Franzon, “Application Exploration for 3-D Integrated Circuis: TCAM, FIFO and FFT Case Studies,” in IEEE Trans. On VLSI, Vol. 17, No. 4, April 2009, pp. 496-506.
  16. P. Mehrotra, P. Franzon, “Optimal Chip Package Codesign for High Performance DSP,” in IEEE Trans. Advanced Packaging, Vol. 28, No. 2, May 2005, pp. 288-297.
  17. M. Aldwairi, T. Conte, P. Franzon, »Configureable string matching hardware for speeding up intrusion detection, » Computer Architecture News 33(1), pp. 99-107.
  18. A.K. Varma, A. Glaser, and P.D. Franzon, “CAD flows for chip-package coverification,” in IEEE Transactions on Advanced Packaging, Vol. 28, No. 1, February 2005, pp. 96-101.
  19. R. Mohan, M.J. Choi, S.E. Mick, F.P. har, K. Chandrasekar, A.C. Cangellaris, P.D. Franzon, M. Steer, “Casual Reduced-order Modeling of Distributed Structures in a Transient Circuit Simulator,” IEEE Trans. MTT, Vol. 52(9), Sept. 2004, pp. 2207-2214.
  20. A.K. Varma, A.W. Glaser, and P.D. Franzon, “CAD Flows for Chip-Package CoVerification,” IEEE Trans. Advanced Packaging, Vol. 28(1), Feb. 2005, pp. 194-202.
  21. J. Xu, L. Luo, S. Mick, J. Wilson, P. Franzon, “AC Coupled Interconnect for Dense 3-D ICs, “AC Coupled Interconnect for Dense 3-D ICs,” in IEEE Transactions on Nuclear Science (TNS). Vol. 51(5), Oct, 2004, pp. 2156-2160.
  22. S.F. Al-sarawi, D. Abbott, and P. Franzon, “A review of 3D Packaging Technology”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Feb. 1998, Vol. 21, No. 1, pp.2-14.
  23. P. Franzon, Andrew Stanaski, Yusuf Tekmen, Sanjeev Banerjia,”System Design Optimization for MCM-D/Flip-Chip”, IEEE Trans. on Components Packaging and Manufacturing Technology, Part B, Vol. 18, 1995, No. 4, pp. 620-627.
  24. P. Franzon, and R. Evans, An MCM Design Process with Application to a Laptop Computer Design , April 1993, Vol. 26, No. 4, pp. 41–49, IEEE Computer Magazine.
PEER REFEREED CONFERENCE PUBLICATIONS
  1. T. -H. Pan, P. D. Franzon, V. Srinivas, M. Nagarajan and D. Popovic, “System Aware Floorplanning for Chip-Package Co-design,” 2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Milpitas, CA, USA, 2023, pp. 1-3, doi: 10.1109/EPEPS58208.2023.10314897.
  2. P. Kashyap et al., “Thermal Estimation for 3D-ICs Through Generative Networks,” 2023 IEEE International 3D Systems Integration Conference (3DIC), Cork, Ireland, 2023, pp. 1-4, doi: 10.1109/3DIC57175.2023.10154977.
  3. J. A. Stevens, T. -H. Pan, P. P. Ravichandiran and P. D. Franzon, “Chiplet Set For Artificial Intelligence,” 2023 IEEE International 3D Systems Integration Conference (3DIC), Cork, Ireland, 2023, pp. 1-5, doi: 10.1109/3DIC57175.2023.10154953.
  4. P. Franzon et al., “Design for 3D Stacked Circuits,” 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 3.5.1-3.5.4. doi: 10.1109/IEDM19574.2021.9720553. Invited Paper.
  5. P. P. Ravichandiran and P. D. Franzon, “A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation,” 2021 IEEE International 3D Systems Integration Conference (3DIC), Raleigh, NC, USA, 2021, pp. 1-6.
  6. L. B. Baker, R. Patti and P. Franzon, “Multi-ANN embedded system based on a custom 3D-DRAM,” 2021 IEEE International 3D Systems Integration Conference (3DIC), Raleigh, NC, USA, 2021, pp. 1-7
  7. T. Nigussie, T. -H. Pan, S. Lipa, W. S. Pitts, J. DeLaCruz and P. Franzon, “Design Benefits of Hybrid Bonding for 3D Integration,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021, pp. 1876-1881
  8. K. Bhanushali, W. Pitts, P. Franzon, “Embedded RFID for Chip Asset Tracking,” in Proc. Gomactech 2021.
  9. T. Nigussie, J. Schabel, S. Lipa, L. McIlrath, R. Patti, P. Franzon, “Design Obfuscation through Smart Partitioning and 3D Integration – Experimental Results,” in Proc. Gomactech 2021.
  10. T. R. Harris, W. R. Davis, S. Lipa, W. S. Pitts and P. D. Franzon, “Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages,” 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan, 2019, pp. 1-3.
  11. S. Dey and P. D. Franzon, “An Application Specific Processor Architecture with 3D Integration for Recurrent Neural Networks,” 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2019, pp. 183-190.
  12. L. B. Baker and P. Franzon, “Multi-ANN embedded system based on a custom 3D-DRAM,” 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 2018, pp. 1-2.
  13. V. Srinivasan et al., “H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor,” 2017 IEEE International Conference on Computer Design (ICCD), Boston, MA, 2017, pp. 145-152.
  14. R. Widialaksono et al., “Physical design of a 3D-stacked heterogeneous multi-core processor,” 2016 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, 2016, pp. 1-5.
  15. S. Dey, P. Franzon, “Design and ASIC Acceleration of Cortical Algorithm for text recognition,” in Proc. IEEE SOCC, Seattle WA, September, 2016
  16. W. Li and P.D. Franzon, “Hardware implementation of Hierarchnical Temporal Memory Algorithm,” in IEEE SOCC, Seattle WA, September 2016.
  17. T. R. Harris et al., “Thermal raman and IR measurement of heterogeneous integration stacks,” 2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Las Vegas, NV, 2016, pp. 1505-1510.
  18. J. Schabel, L. Baker, S. Dey, W. Li and P. D. Franzon, “Processor-in-memory support for artificial neural networks,” 2016 IEEE International Conference on Rebooting Computing (ICRC), San Diego, CA, 2016, pp. 1-8.
  19. T. R. Harris, W. R. Davis and P. Franzon, “Novel packaging and thermal measurement for 3D heterogeneous stacks,” 2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM), Raleigh, NC, 2016, pp. 1-11.
  20. T. Nigussie and P. D. Franzon, “RDL and interposer design for DiRAM4 interfaces,” 2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS), San Diego, CA, 2016, pp. 17-20.
  21. T. R. Harris et al., “Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks,” 3D Systems Integration Conference (3DIC), 2015 International, Sendai, 2015, pp. TS10.2.1-TS10.2.4.
  22. P. D. Franzon et al., “Computing in 3D,” 3D Systems Integration Conference (3DIC), 2015 International, Sendai, 2015, pp. TS6.1.1-TS6.1.2 (invited)
  23. P. Franzon et al., “Computing in 3D,” Custom Integrated Circuits Conference (CICC), 2015 IEEE, San Jose, CA, 2015, pp. 1-6. (invited)
  24. E. J. Wyers, T. R. Harris, W. S. Pitts, J. E. Massad and P. D. Franzon, “Characterization of the mechanical stress impact on device electrical performance in the CMOS and III–V HEMT/HBT heterogeneous integration environment,” 3D Systems Integration Conference (3DIC), 2015 International, Sendai, 2015, pp. TS8.27.1-TS8.27.4.
  25. P. Franzon, et.al. “Computing in 3D”, EDSSC, Singapore, June 2015 (invited)
  26. Priyadarshi, S.; Davis, W.R.; Franzon, P.D., “Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC,” IC Design & Technology (ICICDT), 2014 IEEE International Conference on , vol., no., pp.1,6, 28-30 May 20
  27. Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sunkgwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel “3DEnabled Customizable Embedded Computer (3DECC)” in Proc. 2014 IEEE 3DIC Conference.
  28. T Robert Harris, Lee Wang, Paul Franzon and W Rhett Davis, “Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits.”, in Proc. 2014 IEEE 3DIC Conference.
  29. Randy Widialaksono, Wenxu Zhao, William Rhett Davis and Paul D. Franzon, “Leveraging Leveraging 3D-IC for On-chip Timing Uncertainty Measurements,” in Proc. 2014 IEEE 3DIC Conference.
  30. Franzon, P.D.; Rotenberg, E.; Tuck, J.; Davis, W.R.; Huiyang Zhou; Schabel, J.; Zhang, Z.; Park, J.; Dwiel, B.; Forbes, E.; Joonmoo Huh; Priyadarshi, S.; Lipa, S.; Thorolfsson, T., “Applications and design styles for 3DIC,” Electron Devices Meeting (IEDM), 2013 IEEE International , vol., no., pp.29.4.1,29.4.4, 9-11 Dec. 2013 (invited paper)
  31. Franzon, P.; Bar-Cohen, A., “Thermal requirements in future 3D processors,” 3D Systems Integration Conference (3DIC), 2013 IEEE International , vol., no., pp.1,6, 2-4 Oct. 2013 (Invited Paper)
  32. Franzon, P., “Design and test of 2.5D and 3D stacked ICs,” Electrical Performance of Electronic Packaging and Systems (EPEPS), 2013 IEEE 22nd Conference on , vol., no., pp.vii,vii, 27-30 Oct. 2013
  33. Suh, E.J.; Franzon, P.D., “Design of 60 GHz contactless probe system for RDL in passive silicon interposer,” 3D Systems Integration Conference (3DIC), 2013 IEEE International , vol., no., pp.1,5, 2-4 Oct. 2013
  34. Zhenqian Zhang; Franzon, P., “TSV-based, modular and collision detectable face-to-back shared bus design,” 3D Systems Integration Conference (3DIC), 2013 IEEE International , vol., no., pp.1,5, 2-4 Oct. 2013
  35. Zhenqian Zhang; Noia, B.; Chakrabarty, K.; Franzon, P., “Face-to-face bus design with built-in self-test in 3D ICs,” 3D Systems Integration Conference (3DIC), 2013 IEEE International , vol., no., pp.1,7, 2-4 Oct. 2013
  36. Rotenberg, E.; Dwiel, B.H.; Forbes, E.; Zhenqian Zhang; Widialaksono, R.; Basu Roy Chowdhury, R.; Tshibangu, N.; Lipa, S.; Davis, W.R.; Franzon, P.D., “Rationale for a 3D heterogeneous multi-core processor,” Computer Design (ICCD), 2013 IEEE 31st International Conference on , vol., no., pp.154,168, 6-9 Oct. 2013
  37. Tshibangu, N.M.; Franzon, P.D.; Rotenberg, E.; Davis, W.R., “Design of controller for L2 cache mapped in Tezzaron stacked DRAM,” 3D Systems Integration Conference (3DIC), 2013 IEEE International , vol., no., pp.1,4, 2-4 Oct. 2013
  38. Franzon, P.D., “MOOCs, OOCs, flips and hybrids: The new world of higher education,” Microelectronic Systems Education (MSE), 2013 IEEE International Conference on , vol., no., pp.13,13, 2-3 June 2013 (Invited Paper)
  39. Franzon, P.D.; Priyadarshi, S.; Lipa, S.; Davis, W.R.; Thorolfsson, T., “Exploring early design tradeoffs in 3DIC,” Circuits and Systems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.545,549, 19-23 May 2013 (invited paper)
  40. Karim, M.A.; Franzon, P.D.; Kumar, A., “Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects,” Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd , vol., no., pp.860,866, 28-31 May 2013
  41. Wenxu Zhao; Gadfort, P.; Erickson, E.; Franzon, P.D., “A compact inductively coupled connector for mobile devices,” Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd , vol., no., pp.2385,2390, 28-31 May 2013
  42. Priyadarshi, S.; Choudhary, N.K.; Dwiel, B.; Upreti, A.; Rotenberg, E.; Davis, R.; Franzon, P., “Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors,” Quality Electronic Design (ISQED), 2013 14th International Symposium on , vol., no., pp.1,7, 4-6 March 2013
  43. Franzon, P.D.; Priyadarshi, S.; Lipa, S.; Davis, W.R.; Thorolfsson, T., “Exploring early design tradeoffs in 3DIC,” Circuits and Systems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.545,549, 19-23 May 2013
  44. G Charles, P. Franzon, “Comparison of TSV-based PDN design effects using various tacking topology methods,” in Proc. 21st EPEPS, 2012, pp. 83-86.
  45. P. Franzon, W. Davis,. Z. Zhen, S. Priyadarshi, M. Hogan, T. Karnik, G. Srinivas, “Coordinating 3D designs: Interface IP, standards or free-form?,” in Proc. 2011 IEEE 3DIC Conference, 2012. Invited Paper.
  46. N. DiSpigna, D. Schinke, S. Jayant, V. Misra, and P. Franzon, “A novel double floating-gate unified memory device,” in 20th IEEE/IFIP VLSI-SOC, pp. 53-58. 2012. Won Conference Best Paper Award.
  47. Z. Yan, C. Won, P. Franzon, K. Aygun, H. Braunisch, “S-parameter based multimode signaling,” in Proc. 21st EPEPS, pp. 11-14, 2012.
  48. S. Priyadarshi, J. Hu, W. Choi, S. Melamed, X. Chen, W. Davis, P. Franzon, “Pathfinder 3D: A flow for system level design space exploration,” in Proc. 2011 IEEE 3DIC Conference, January, 2012.
  49. T. Thorolfsson, S. :Lipa, P. Franzon, “A 10.35 mW/GFLOP stacked SAR DSP unit using fine-grain partitionined 3D integration,” in 2012 IEEE CICC, pp. 1-4, 2012.
  50. P. Gadfort, P. Franzon, “Design, modeling and fabrication of mm3 three-dimensional integrated antennas,” in Proc. 62nd IEEE ECTC, pp. 1794-1799, 2012.
  51. P. Gadfort, P. Franzon, “Near threshold RF-only analog to digital converter,” in IEEE SubVT Conference, pp. 1-3, 2012.
  52. P. Franzon, En-Xiao, “Design Strategies for Chip/Package Codesign,” in Proc. 2011 IEEE EPEPS, 2011, pp. 15-16.
  53. P.D. Franzon, W.R. Davis, T. Thorolfsson, S. Melamed, “3D Specific Systems: Design and CAD,” in 20th Asian Test Symposium, 2011, pp. 470-473. (Invited).
  54. X. Chen, W.R. Davis, P.D. Franzon, “Adaptive Clock Distribution for 3D Integrated Circuits,” in Proc. 2011 IEEE EPEPS, 2011, pp. 91-94.
  55. P.D. Franzon, W.R. Davis, T. Thorolfsson, S. Melamed, “3D Specific Systems Design and CAD,” in 2011 Int. Conf on Embedded Computer Systems,” 2011, pp. 326-329.
  56. G. Charles, P.D. Franzon, J. Kim, A. Levin, “Analysis and approach of TSV-based hierarchical power distribution for estimating 1st droop and resonant noise in 3DIC,” in 2011 IEEE EPEPS, 2011, pp. 267-270.
  57. P. Franzon, J. Wilson, L. Ming, “Thermal Isolation in 3D Chip Stacks Using Vacuum gaps and Capacitive or Inductive Communications,” in IEEE 3DIC 2010, pp.1-4.
  58. S. Lipa, T. Thorolfsson, and P. Franzon, “The NCSU Tezzaron Design Kit,” in IEEE 3DIC 2010, pp. 1-15.
  59. T. Thorolfsson, L Guojie, J. Cong, and P. Fraqnzon, “Logic-on-logic 3D Integration and Placement,” in IEEE 3DIC 2010, pp. 1-4.
  60. S. Melamed, T. Thorolfsson, A. Srinivasan, E. Cheng, P. Franozn and W.Davis, “Thermal Investigatoin of Tier Swapping to Improve the Thermal Profile of Memory-on-Logic 3DICs,”, in IEEE THERMINIC 2010, pp. 1-6.
  61. S. Melamed, T. Thorolfsson, A. Srinivasan, E. Cheng, P. Franzon, R. Davis, “Junction Level Thermal Extraction and Simulation of 3DICs,” in Proc. IEEE 3D System Integration Conference, September, 2009.
  62. T. Thorolffson, K. Gonsalves, P.D. Franzon, “Design Automation of a 3DIC FFT Processor, for Synthetic Aperture Radar: A case study,” in Proc. ACM/IEEE DAC 2009, pp. 51-56.
  63. M. Tsai, A. Klooz, A. Leonard, J. Appel, P. Franzon, “Through Silicon Via (TSV) defects/pinhole self test circuit for 3D-IC,” in Proc. IEEE 3D System Integration Conference, September, 2009.
  64. E. Oh, P. Franzon, “Technology Impact Analysis for 3D TCAM,” in Proc. IEEE 3D System Integration Conference, September, 2009.
  65. P. Gadfort, P.D. Franzon, “Low-power self-equalizing driver for silicon carrier interconnects with low bit-error rate,” in Proc. IEEE EPEPS, Oct. 2009, pp. 37-40.
  66. P. Franzon, W. Davis, T. Thorolffson, “Creating 3D Specific systems: Architecture, design and CAD,” in Proc. DATE 2010, pp. 1684-1688. Invited Paper.
  67. T
  68. P. Franzon, W. Davis, M. Steer, T. Thorolfsson, L. McIlrath, and K. Obermiller, “CAD and Design Application Exploration of 3DICs,” in Proc. 2008 Gomactech, April 2009.
  69. M. Hamlett, L. McIlrath, F. Kiamilev, V. Ozguz, ”CryptoFSM – Securing chips against reverse engineering,” in Proc. 2008 Gomactech, April 2009.
  70. N. DiSpigna, P. Chakraborti, P. Yang, T. Ghosh, and P. Franzon, “Application of EAP materials towards a refreshable Braille display,” in Proc. SPIE 3275, (9 pp) April 2009.
  71. P. Franzon, S. Lipa, E. Oh, T. Thorolfsson and W.R. Davis, ”Memory rich applicatons for 3D integration,” in Proc SPIE 7268, Smart Structures, Devices and Systems IV, Dec. 2008, (5 pp) Invited Paper.
  72. Paul D. Franzon, William Rhett Davis, Michael B. Steer, Hua Hao, Steven Lipa, Sonali Luniya, Christopher Mineo, Julie Oh, Ambirish Sule, Thor Thorolfsson, “Application and Design Exploration for 3D Integrated Circuits,” VLSI Multi-level Interconnect Conference, September 2008, Invited paper.
  73. W.R. Davis, A.M. Sule and P.D. Franzon, “An 8192-point fast fourier transform 3D-IC case study, in Proc. 51st Midwest Symposium on Circuits and Systems, Aug. 2008, pp. 438-441.
  74. B. Su, P. Patel, S.W. Hunter, M. Cases, and P.D. Franzon, “AC coupled backplane communication using embedded capacitor,” in IEEE EPEP 2008, Oct. 2008, pp. 295-298.
  75. R. Puri, D. Varma, D. Edwards, P. Franzon, S. Kosonocky, A>J. Weger, A. Yang, “Keeping hot chips cool: are IC thermal problems hot air?”, in Proc. IEEE DAC, pp. 634-5, June 2008.
  76. P.D. Franzon, et.al., “Design and CAD for 3D Integrated Circuits”, IEEE/ACM Design Automation Conference, June 2008. (Invited Session). pp. 668-673.
  77. P. D. Franzon, et.al., “Computer-Aided Design and Application Exploration for 3D Integrated Circuits,” in GOMACTECH, April, 2008.
  78. Paul D. Franzon, William Rhett Davis, Michael B. Steer, Hua Hao, Steven Lipa, Sonali Luniya, Christopher Mineo, Julie Oh, Ambirish Sule, Thor Thorolfsson, “Application and Design Exploration for 3D Integrated Circuits,” VLSI Multi-level Interconnect Conference, September 2007, Invited paper.
  79. T. Thorolfsson, P.D. Franzon, “System Design for 3D Multi-FPGA Packaging,” in IEEE Electrical Performance of Electronic Packaging, 2007, Oct, 2007, pp. 171-174.
  80. A. Varma, M. Steer, P. Franzon, “System level Validation of Improved IO Buffer Behavioral Modeling Methodology Based on IBIS,” in IEEE Electrical Performance of Electronic Packaging, 2007, Oct, 2007, pp. 351-354.
  81. E.C Oh, P.D. Franzon, “Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory, in IEEE CICC, Sept. 2007, pp. 591-594.
  82. P.D. Franzon, W.R. Davis, M.B. Steer, H. Hao, S. Lipa, C. Mineo, J. Oh, A. Sule, T. Thorolfsson, “Design for 3D Integration an Applications,” ISSSE ’07, August, 2007, pp. 263-266. Invited Paper.
  83. O-E Chu, P. Franzon, “TCAM core design in 3D IC for low matchline capacitance and low power,” Proc. SPIE Smart Structures, Devices and Systems III, 2006, Invited Paper, pp. 641-5.
  84. J. Xu, J. Wilson, S. Mick, L. Luo,“2.8 Gbps inductively coupled interconnect for 3D ICs,” 2005 symposium on VLSI circuits, June 2005, pp. 352-355.
  85. K. Chandrasekar, Z. Feng, J. Wilson, S. Mick, P. Franzon,“Inductively Coupled Board to Board Connectors,“ ECTC’05, 31 May – 3 June, 2005, pp. 1109-1113.
  86. J. Xu, J. Wilson, S. Mick, L. Luo and P. Franzon, “2.8 Gb/s Inductively Coupled Interconnect for 3-D ICs,” in Japan VLSI Symposium, June, 2005.
  87. Jian Xu, Stephen Mick, John Wilson, Lei Luo, Karthik Chandrasakhar, Paul Franzon, “AC Coupled Interconnect for Dense 3-D Systems”, Proc. IEEE Conference on Nuclear Science and Imaging, Seattle Washington, October 2003.
  88. M. Nakkar, A.W. Glaser, P. Franzon, K. Williams, M. Roberson, G. Rinne, “Three Dimensional MCM Package Assembly and Analysis,” in Proc. IEEE/IMAPS Conference on High Density Packaging and MCMS, Denver, CO., May 1999, pp. 188-192.
  89. J.T. Schaffer, S.Lipa, A. Glaser, P. Franzon, “Issues in Chip-Package Codesign with MCM-D/Flip-Chip Technology”, Proc. IEEE International Symposium on Chip-Package Codesign , Feb. 1998, pp 88-92.
  90. A.W. Glaser, M. Nakkar, P.D. Franzon, T.M. Conte G. Rinne, M. Roberson, V. Rogers, C.K. Williams, “A Low-cost, High Performance Three-Dimensional Memory Module”, in Proc. IEEE Memory Technology, Design and Testing Workshop, August 1997.
  91. Mouna Nakkar, Paul Franzon, A.W. Glaser, V Rogers, K.C. Willimas, and Glenn Rinne, “Thermal/mechanical analysis and design of three dimensional high density MCM package”, in Proc. Next Generation Package Design Workshop, June 11 1997.
  92. M. Azam, P. Franzon, T. Conte, “Low Power Data Processing by Elimination of Redundant Computations”, in Proc. 1997 International Symposium on Low Power Electronics and Design, Aug 18–20th, Monterey, California, pp.259-264.
  93. Glaser, A.; Nakkar, M.; Franzon, P.; Rinne, G.; Roberson, M.Rogers, V.; Williams, C.K.;“A low cost, high performance three-dimensional memory module”, Proc. Int. Workshop Memory Technology, Design and Testing, 1997. Page(s): 2 -7.
  94. Toby Schaeffer, Alan Glaser, Steve Lipa and Paul Franzon, MCM Implementation of a Data Encryption Standard (DES) Processor ,in Proc. 1997 IEEE MCM Conference, Feb. 1997, pp.13-17.
  95. Wes Hansford Jennifer Peltier, Paul Franzon, Steve Lipa, and Jonathan Schaeffer, MIDAS Flip-Chip Service , in Proc. 1997 IEEE MCM Conference, Feb. 1997,pp.133-135.
  96. Paul D. Franzon, Tom Conte, Sanjeev Banerjia, Alan Glaser, Steve Lipa, Toby Schaffer, Andrew Stanaski and Yusuf Tekmen, Computer Design Strategy for MCM-D/Flip-Chip Technology, in Proceedings 1996 Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 1996, pp.6-8..
  97. P. Franzon, Computer Design Strategy for MCM-D/Flip-Chip Technology, Invited paper, in Proceedings 1996 ASIC Conference, Oct. 1996, pp35-39.
  98. P. Franzon, System Design Optimization With Multichip Module Technology, Invited Paper, in Proceedings 1996 Conference of the Brazilian Microelectronics Society, July 1996.
  99. Christoforos Harvatis, Yusuf C. Tekmen, Grif L. Bilbro, Paul D. Franzon, Pin Assignment for High-Performance MCM Systems, in Proceedings 1996 IEEE ISCAS Conference. pp. 771-774.
  100. Sanjeev Banerjia, Alan Glaser, Christoforos Harvatis, Steve Lipa, Real Pomerleau, Toby Schaffer, Andrew Stanaski, Yusuf Tekmen, Grif Bilbro, and Paul Franzon, Issues in Partitioning Integrated Circuits for MCM-D/Flip-Chip Technology, in Proceedings 1996 IEEE MultiChip Module Conference.
  101. P. Franzon, Optimal System Design with MultiChip Module Technology, Invited Paper, in Proceedings of Microeletronics’95.
  102. A
  103. Paul Franzon, Andrew Stanaski, Yusuf Tekmen, Sanjeev Banerjia, “System Design Optimization for MCM”, in Proc. 1995 IEEE MultiChip Module Conference.
  104. S. Mehrotra, P. Franzon, G. Bilbro and M. Steer, CAD tools for Managing Signal Integrity and Congestion Simultaneously, Proc. 1994 Topical Meeting on Electrical Performance of Electrical Packaging, pages 30-32.
  105. D. Winick, M. Teague, and P. Franzon, Applications of MEMS to Reconfigurable Free Space Optical Interconnect, Proc. NSF Optical Packaging Workshop, Breckenridge CO, August 15-17, 1994.
  106. M. Steer, S. Lipa, and P. Franzon, Experimental characterization of interconnects and discontinuities in thin-film multichip module substrates, in Proc. 1993 IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Monterey CA, October 20–22.
  107. Paul Franzon, Slobodan Simovich, Sharad Mehrotra, Michael Steer, Macromodels for Generating Signal Integrity and Timing Management Advice for Package Design, in Proc. IEEE 1993 ECTC Conference. pp. 523-529.
  108. Paul Franzon, Slobodan Simovich, Sharad Mehrotra and Michael Steer, Automatic A-Priori Generation of Delay and Noise Macromodels and Wiring Rules for MCMs, IEEE 1993 MCM Conference.
  109. Slobodan Simovich and Paul Franzon, A simple method for noise tolerance characterization of digital circuits , Proc. 1993 Great Lakes VLSI Conference.
  110. Todd A. Cook, Ed Harcourt, Thomas K. Miller III, and Paul D. Franzon: Beharvioral modeling of processors from instruction set specifications, to appear in the Open Verilog International 1993 Conference.
  111. J. Bowen, D. Bahler, and P. Franzon, Design advice systems for concurrent engineering: A constraint-based approach, NSF Grantees Conference, Charlotte NC, Jan 93.
  112. P.D. Franzon, S. Simovich, M. Steer, M. Basel, S. Mehrotra, and T.D. Mills, “Tools to aid in Wiring Rule Generation for High Speed Interconnects”, Proc. 1992 Design Automation Conference, pp.466-471.
  113. P.D. Franzon, M. Mehrotra, S. Simovich, and M. Steer: Automating Design for Signal Integrity}, 1992 IEEE Topical Meeting on Electrical Performance of Electronic Packaging,Tuscon AZ, Proc. pp.10–13.
  114. M. Steer and P.D. Franzon: Microwave characterization of thin-film multi-chip module substrates and printed wiring boards accounting for frequency-dependent characteristic impedance, 1992 IEEE Topical Meeting on Electrical Performance of Electronic Packaging,Tuscon AZ, Proc. pp.125-127.
  115. E.J. Vardaman and M.W. Hartnett and L.H. Ng and P.D. Franzon, “Cost/performance issues in multichip module packaging”, Proc. Japan Int. Conf. on Microelectronics, 1992.
  116. Paul Franzon, Sharad Mehrotra, Slobodan Simovich, Michael Steer, “Automating Design for Signal Integrity”, Topical Meeting on Electrical Performance of Electronic Packaging,Tucson, Arizona, April 23, 1991.
  117. Paul Franzon, Michael Steer, Ronald Gyurcsik, Tools and echniques for the Design of High Speed Multichip Modules Proc. Japan IEMT, July, 1991.
  118. D. Van den Bout, T. Nagle, T. Miller and P. Franzon, The NCSU Design Center, in Proc 1991 Microsystems Educators Conference, July 1991, San Jose CA.
  119. P.D Franzon and M.B. Steer, Interconnect Modeling and Simulation for High Speed MCM, in Proc. Multichip Module Workshop, March 28th-29th, 1991, pp. 122–129.
  120. P. Franzon and Michael Steer: Tools and Techniques for the Design of High Speed Multichip Modules , in Proc. Third Annual Electronics Packaging Symposium,May 13 -14, 1991, Binghamton NY.
  121. P. Franzon, et al: CAD Tools for the Automated Design of High Speed Multichip Modules, Proceedings of the 1990 International Packaging Symposium.