Research

Design of 3D ICs

3D and 2.5D integration gives improvements in Power, Performance Area and Cost equivalent to a generation of Moore’s Law.  Projects include design and design automation for 2.5D and 3D systems including chipletized systems as well as the investigation of Heterogeneous Integration.

Applying Machine Learning to Electronics Design Automation

This work covers a variety of problems from fast DRC checking to generating layouts.  Most (but not all) of this work is done through the Center for Advanced Electronics through Machine Learning (CAEML).


 Link to CAEML home page

Related work: https://arxiv.org/abs/2406.13808

RFID

We have designed and built the world’s smallest RFID tag chip.  We are exploring applications in securing the semiconductor supply chain. 

Past Projects

Here is a listing of my other completed projects with my past students:

  • 3DIC and interposer (2.5D) design: The design, and CAD support, for 3D (stacked) ICs and multi-chip packages, spanning architecture, CAD, test, validation and circuit design. Read more
  • Cortical Processing and Hardware for Machine Learning. Investigations into hardware concepts that can be used to implement cortically inspired and machine learning functions. Read more
  • Center for Advanced Electronics through Machine Learning (CAEML). This Industry/Government/University Center focues on applying Machine Learning to problems in electronics design. This program is joing with UIUC and Ga Tech. Read more
  • AC powered circuits for RFID. Digital and analog circuits that can be powered off an AC supply. We are primarily exploring target applications in RFID. Read more
  • IRDS. Links to my activities as part of the International Roadmap for Devices and Systems (IRDS), formerly International Technology Roadmap for Semiconductors (ITRS). I am the editor of the Emerging Resarch Arhicitectures section of the Emerging Research Devices chpater. This site includes presentations at workshops I ran. Read more
  • Unified Memory Device. A new “unified” memory device that permits both a volatile bit and a non-volatile . (Completed Project.) Read more
  • Multimode Interconnect. Coding scheme to permit dramatic crosstalk reduction in electronic chip to chip interconnect. This in turn leads to dramatic reductions in packaging cost. (Completed Project.) Read more
  • AC Coupled Interconnect. Contactless, high bandwidth, highd-density, low-cost and low-power packaging structures and circuits for chip packaging, sockets and connectors. (Completed Project.) Read more
  • Hardware Acceleration for Automated Speech Recognition. Building accelerators for critical steps in speech recognition leads to dramatic improvements in power consumption, and performance. This project has morphoed into a broader project on cortical processing. (Completed Project.) Read more
  • Refreshable Braille Display. A full page refreshable tactile display based on ElectroActive Polymers. This project has been spun out of the Univesrity as Polymer Braille Inc. (Completed Project.)
  • CAD for self-calibrating circuits. Computer Aided Design techniques to support the deisign Digital and analog circuits that can be powered off an AC supply. We are primarily exploring target applications in RF. This project has morphed into our activities within CAEML. Read more
  • On-chip interconnect. Using on-chip equalization for the design of low-power repeaterless global on-chip interconnect. Past work includes other techniques for low-power interconnect design, and development of on-chip measurement techniques. This project has morphed into my 2D and 3D projects. (Completed Project.) Read more
  • Network processor codesign. Methdologies and archictures for networking, mainly network security. (Completed Project.) Read more
  • Chip-package codesign. Methdologies and tools for codesign of chips, packages, and multichip modules. Includes ongoing support for IO macromodeling, including Spice2Ibis. (Now part of CAEML.) Read more

Publications