A list of students whose Doctoral Theses were directed under my supervision

1. Priyank Kashyup, “Machine Learning to enable Side-Channel Analysis and Generative Modeling in Electronic Design Automation “, 2023, CoChair
2. Archit Gajjar, “Ransomware Detection with XGBoost Hardware Acceleration for Data Centers using High-Level Synthesis”, 2023, Chair
3. Luis Francisco, “Machine Learning for Design Rule Checking, Multilayer CMP Hotspot Detection, using Transfer Learning and Synthetic Training”, May 2022, co-Chair..
4. Billy Huggins, “An Evolutionary Approach to Producing Optimal Electronic Design Automation Tool Settings”, May 2021, co-chair.
5. Theodros Nigussie, “Design obfuscation throught smart partitioning and 3D integration,”, Mar. 2020, chair.
6. Kirti Bhanashuli, “On implementing power-efficient and scalable short-range RF-power radios using RF-only architectures,” Jan., 2020, chair.
7. Yi Wang, “Solving Inverse Problem through optimization and its application to Analog/RF Design,” March 2020, chair.
8. Bowen Li, “High-speed receiver behavioral modeling using machine learning,”, Jan. 2020, chair.
9. Sumon Dey, “Design of a scalable, confirugate and cluster-based hierarchical hardware accelerator for a cortically inspired algorithm and recurrent neural networks,” August, 2019, chair.
10. Weifu Li. Design of Hardware Accelerators for Hierarchical Temporal Memory and Convolutional Neural Networks”, August 2019, chair.
11. Nazia Zannat, “Design of contactless connectors for simultaneous power and data transfer,” May, 2019, chair.
12. Zhao Wang, “Efficient linear matrix solver and its hardware implementations dedicated to faster than real time dynamic simulation of large scale power systems,” September, 2018, chair.
13. Lee Baker, “Design of a 3DIC system to aid in the acceleration of embedded system that employ multiple instances of disparate artificial neural networks,” March 2018, chair.
14. Jong Beom Park, “A circuit level three-dimensional DRAM area timing and energy model,” March 2018, co-chair.
15. Josh Schabel, “Design of an application specific instruction set processor for sparse neural networks,”, October 2017, chair.
16. Weiyi Qi, “IC Design Analysis, Optimization and Reuse via Machine Learning, August, 2017, Chair.
17. Wenxu Zhao, “RF-only Logic Enbabled RFID Transponder Size Reduction,”, December 2016.  Chair.
18. Marcus Tshibangu, “Study and analysis of Energy Efficient DRAM Cache with unconventional row buffer size,” August 2016.  Chair.
19. Randy Widialaksono, “Three Dimensional Integration of Hterogeneous Multi-Core Processors,” June, 2016.  Co-chair.
20. Zhenquian Zhang, “Design of On-chip bus of Heterogeneous 3DIC Micro-processors,” May 2016, Chair.
21. Sarkar, Biplap, “Atomic Layer Deposition Techniques for Novel Memory Applications,” August 2015. Cochair
22. Winick, David, “Electroactive Polymer Refreshable Braille Display, December 2015 (Posthumous).
23. Gary Charles, “Design, Model and Analysis of TSV-based On-Chip PDN Interconnects for 3-D Integrated Circuits. “, March 2015.
24. Zhao Yan, “S-Parameter Based Binary Multimode Interconnect Design Methodology and Implementation,” December, 2014 .
25. W.S. Pitts, “High quality CMOS Integratable Varactors,” March 2014.
26. Peter Gadfort, “Packaging and Integration of Three Dimensional Microsensors,” December, 2013.
27. Evan Erickson, “Multi-Gbps Inductively Coupled Connectors,” December, 2013.
28. Akalu Lentiro, “Low-Density, Ultra-Low Power and Smart Radio Frequency Telemetry Sensor,” October, 2013.
29. Shivam Priyadarshi, “System and Gate Level Dynamic Electrothermal Simulation of Three Dimensional Integrated Circuits,” June, 2013.
30. Eric Wyers, “Direct Search Calibration Algorithms for Digitally Reconfigurable Radio Frequency Integrated Circuits,” March 2013.
31. Ojas Ashok BOpat, “A Generic Scalable Architecture For a Large Acoustic Model and Large Vocabularly Speech Recognition Accelerator,” October, 2012.
32. Won Hao Choi, “System Level Power Prediction Methodology for Mobile 3-D Graphic Engines,” May 2012.
33. Hsuan-Jung Su, “Continuous-Time Fractionally Spaced Equalization and Its Application in Capacitively Coupled Chip-To-Chip Interconnect,” May, 2012.
34. Matthew Hamlett, “A Novel Approach to IP Protection Using Automated Hardware Techniques to Secure a Design,” March 2012.
35. Mustafa Berke Yelten, “Variability and Reliability in Nanoscale Circuits: Simulation, Desgin, Monitoring and Characterization,” January, 2012.
36. Hoon Seok Kim, “Advanced Multi Mode Interconnect,” December, 2011.
37. Xiangzhong Xue, “Electronic System Optimization Via Convex Programming,” December, 2011.
38. Tsing Zhu, A Surrogae Model-based Framework for Design and Macromodeling of Self-calibrated Analog Circuits,” October, 2011.
39. Chanyoun Won, “Multimode Interconnect for High-Density Links: Implementation, Design Methodology and New Crosstalk Cencallation Scheme,” July 2011
40. Thor Thorolfsson, “Three Dimensional Integration of Synthetic Aperture Radar Processors,” April 2011
41. Daniel Schinke, “Computing with Novel Floating Gate Devices,” April 2011
42. Yongjin Choi, “Design of Multimodel Signaling Transceiver for High-Density and High-Speed Links,” May 2010.
43. Eun Chu Julie Oh, Ph.D. Dissertation, “Design and Applications of Three-Dimensional Circuits”, December, 2009.
44. Karthik Chandrashekhar, Ph.D. Dissertation, “Inductively Coupled Connectors,” December, 2008
45. Dhruba Chandra, Ph.D. Dissertation, Speech Recognition CoProccessor, December, 2007.
46. Meeta Yadav, “Hardware Architecture of behavior Modeling Coprocessor for Network Intrusion Detection,” Ph.D. Dissertation, March, 2007.
47. Ullas Pazhayaveetil, “Hardware Implementation of a Low Power Speech Recognition System,” Ph.D. Dissertation, February, 2007.
48. Jian Xu, “AC Coupled Interconnect for Inter-Chip Communications,” Ph.D. Dissertation, December, 2006.
49. Ambrish Varma, “Improved behavioral modeling based on Input Output Buffer Information Specification,” Ph.D. Dissertation, NCSU, October, 2006.
50. Sachin Sonkusale, “Planar edge defined alternate layer process (PEDAL) – an unconventional technique for the fabrication of wafer scale sub-25 nm nanowires and nanowire template,” PhD, October, 2006.
51. Liang Zhang, “Driver Pre-emphasis Signaling for on-chip global interconnects,” Ph.D. Dissertation, September, 2006.
52. Monther Al Dwairi, “Hardware Efficient Pattern Matching Algorithms and Architectures for Fast Intrusion Detection,” Ph.D., November, 2006.
53. John Damiano, “Active body bias for low-power silicon-on-insulator design,” Ph.D., March 2006.
54. Neil DiSpigna, “Electronic Devices and Interface Strategies for Nanotechnology,” Ph.D., April 2006.
55. Christian Amsinck, “Molecular Electronic Memories,” Ph.D., March 2006.
56. Lei Luo, “Capacitively Coupled Chip to Chip Interconnect Design, Ph.D., December, 2005.
57. Leon Zhang, “Driver pre-emphasis signaling for on-chip global interconnects,” Ph.D., December, 2005.
58. Steve Lipa, “Phase Noise Analysis of Rotary Oscillators,” Ph.D. May 24, 2005
59. David Nackashi, Circuit and Integration Technologies for Molecular Electronics, Ph.D.  2004
60. Stephen Mick, AC Coupled Interconnect, Ph.D.  200
61. John Wilson, Linearly Tunable RF MEMS Capacitors Implemented Using an Integrated Removable Self-Masking Technique, Ph.D.  2004
62. Andrew Stanaski, Sensor Circuits for Flip Chip Debug, Ph.D.  2004
63. Pronita Mehrotra, High Performance Hardware Memory Algorithms, Ph.D.  2003
64. Bruce Duewer, MEMS Switch Fabric, Ph.D.
65. Toby Schaffer, Chip-package Codesign, Ph.D.
66. Mouna Nakkar, Dynamically Programmable Cache, Ph.D.
67. Mir Azam, Custom CMOS Design and Architecture for Low-Power High-Performance Circuits, PhD.
68. Debu Ghosh (co-chair), Synthesis of Benchmarking Expiriments, Ph.D.
69. Chris Harvatis, Performance Driven Partitioning for MCMs, PhD.
70. Slobodan Simovich, Computer-Aided Analysis of Interconnect,PhD.
71. Scott Washabaugh, Low energy FSM Design, PhD.
72. Sharad Mehrotra, Automated Synthesis of High Speed Digital Circuits and Package-Level Interconnect, PhD.
73. Todd Cook, Instruction Set Architecture Specification, PhD.
74. Robert Evans, Energy Consumption for Modeling and Optimization of SRAMs, PhD.